PIPELINE ARRAY IMPLEMENTATION OF FIR FILTERS (WedPmPO1)

Author(s) : Paraskevas Kalivas (National Technical University of Athens, Greece) Paul Bougas (National Technical University of Athens, Greece) Vassilis Vassilakis (National Technical University of Athens, Greece) Christos Meletis (National Technical University of Athens, Greece) Kiamal Pekmestzi (National Technical University of Athens, Greece)

Abstract : A new pipeline array type parallel scheme for the implementation of FIR digital filters of low-latency is presented in this paper. Each cell of the array of the proposed scheme implements the computation of a one-bit FIR filter and is based on carry-save arithmetic. This structure leads to a low-latency implementation that is independent of the number of the filter taps. The proposed scheme is pipelined at the bit-level, requires less hardware and yields superior performance than other schemes that are based on discrete multipliers. Also, a merging technique is applied inside the one-bit FIR filter cell achieving systolicity at the bit-level.

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