AN OPTIMISED SYSTOLIC ARRAY-BASED MATRIX INVERSION FOR RAPID PROTOTYPING OF KALMAN FILTERS IN FPGA’S (FriAmPO2)

Author(s) : Yat Tin Lai (The University of Auckland, New Zealand) Abbas Bigdeli (The University of Auckland, New Zealand) Morteza Biglari-Abhari (The University of Auckland, New Zealand)

Abstract : In this paper we propose a pipelined structure for systolic array-based matrix inversion. The main focus is to optimise the systolic structure for rapid prototyping of Kalman filters in FPGA devices. The design is implemented in VHDL lan-guage enabling potential users to effectively customise the structure for different size Kalman filters suitable for differ-ent applications. The proposed solution consists of pipeline registers, an innovative logic control unit, and a segmented Look Up Table based division scheme. The new architec-ture has an advantage of O(2n) resource consumption, com-pared to the O(n2) in other systolic array structures. The re-sulting precision error is within an acceptable range.

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