C-BASED HARDWARE DESIGN OF IMDCT ACCELERATOR FOR OGG VORBIS DECODER (ThuAmPO2)

Author(s) : Shinichi Maeta (Osaka University, Japan) Atsushi Kosaka (Osaka University, Japan) Akihisa Yamada (Sharp Corporation, Japan) Takao Onoye (Osaka University, Japan) Tohru Chiba (Sharp Corporation, Japan) Isao Shirakawa (Osaka University, Japan)

Abstract : This paper presents hardware design of an IMDCT accelerator for an Ogg Vorbis decoder using a C-based design system. Low power implementation of audio codec is important in order to achieve long battery life of portable audio devices. Through the computational cost analysis of the whole decoding process, it is found that Ogg Vorbis requires higher operation frequency of an embedded processor than MPEG Audio. In order to reduce the CPU load, an accelerator is designed as specific hardware for IMDCT, which is detected as the most computation-intensive functional block. Realtime decoding of Ogg Vorbis is achieved with the accelera-tor and an embedded processor both run at 36MHz. The operation frequency is at the same level as that of MPEG Audio decoding process by an embedded processor.

Menu