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Paper data
Multiplierless implementation of all-pole digital filters using a low-sensitivity structure

Bhattacharya Mrinmoy, Institute of Signal Processing, Tampere University of Technology
Saramäki Tapio, Institute of Signal Processing, Tampere University of Technology

Page numbers in the proceedings:
Volume I pp 687-690

Filter Design

Paper abstract
Multiplierless filters are natural extensions of the low-sensitivity structures. Some low-sensitivity structures are associated with structural alteration and the resulting multiplier coefficients are different than the initial designed values in these structures. For the cases when coefficient values are quite small, they can be implemented in a multiplierless manner, i.e., by using only few bit shifts and adds and/or subtracts, by converting them to minimum signed powers-of-two (MNSPT) or canonic signed digit (CSD) forms, and the number of nonzero bits required for coefficient representations are quite low. This paper investigates a low-sensitivity unconventional structure that is very suitable for implementing all-pole digital filters. Further, accepting a marginal deviation from the given specifications, the required number of nonzero bits becomes very low, making the overall implementation attractive. Also, one can start with a filter with marginally stricter specifications without increasing the filter order. Then, the modified coefficient values are quantized such that the given overall criteria are still met.

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