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Paper data
A Low-Power VLSI Architecture for Face Verification Using Elastic Graph Matching

Nagel Jean-Luc, IMT, University of Neuchâtel
Stadelmann Patrick, IMT, University of Neuchâtel
Ansorge Michael, IMT, University of Neuchâtel
Pellandini Fausto, IMT, University of Neuchâtel

Page numbers in the proceedings:
Volume III pp 577-580

Low-Power Algorithms / Architectures for Image and Video

Paper abstract
This paper introduces a novel low-power VLSI architecture dedicated to algorithms based on elastic graph matching. The targeted application is face verification for low-power mobile devices (e.g. mobile phones, personal digital assistants, wearable computing devices). A description of the overall verification system is provided jointly to a detailed discussion of the full-custom graph matching coprocessor.

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