Session :

ThursPM4. Implementation

Date: Thursday, 08 November 2007
Time: 16:35 - 18:00

Efficient and Accurate Implementation of Image Scaling in the Frequency Domain (Abstract)

Arianne T. Hinds	(InfoPrint Solutions Company, United States)
Nenad Rijavec	(InfoPrint Solutions Company, United States)
Joan L. Mitchell	(InfoPrint Solutions Company, United States)

Pipelining Architecture Design of the H.264/AVC HP@L4.2 Codec For HD Applications (Abstract)

Kiwon Yoo	(Samsung Electronics, South Korea)
Kwanghoon Sohn	(Yonsei University, South Korea)

New LZW Data Compression Algorithm and Its FPGA Implementation (Abstract)

(Beijing Institute of Technology, China)

A Cost-Efficient Residual Prediction VLSI Architecture for H.264/AVC Scalable Extension (Abstract)

Yi-Hau Chen	(National Taiwan University, Taiwan)
Tzu-Der Chuang	(National Taiwan University, Taiwan)
Chuan-Yung Tsai	(National Taiwan University, Taiwan)
Yu-Jen Chen	(National Taiwan University, Taiwan)
Liang-Gee Chen	(National Taiwan University, Taiwan)

Algorithm and Architecture Design for Intra Prediction in H.264/AVC High Profile (Abstract)

Tzu-Der Chuang	(National Taiwan University, Taiwan)
Yi-Hau Chen	(National Taiwan University, Taiwan)
Chen-Han Tsai	(National Taiwan University, Taiwan)
Yu-Jen Chen	(National Taiwan University, Taiwan)
Liang-Gee Chen	(National Taiwan University, Taiwan)

FLEXBLE ARCHITECTURE OF PROCESSOR OPTIMIZED FOR MULTIMEDIA APPLICATIONS (Abstract)

Adam Luczak	(Poznan University of Technology, Poland)
Olgierd Stankiewicz	(Poznan University of Technology, Poland)

Area-efficient Quantization Architecture with Zero-prediction Method for AVS Encoders (Abstract)

Ke Zhang	(Institute of Information and Communication Engineering, Zhejiang University, China)
Yunpeng Zhu	(Institute of Information and Communication Engineering, Zhejiang University, China)
Lu Yu	(Institute of Information and Communication Engineering, Zhejiang University, China)

PARALLEL VARIABLE LENGTH DECODING WITH INVERSE DISCRETE COSINE TRANSFORM ON VLIW DSP (Abstract)

(ITRI/STC, Taiwan)

VLSI Architecture of H.264 RDO-based Block Size Decision for 1080 HD (Abstract)

Ryoji Hashimoto	(Osaka University, Japan)
Kimiya Kato	(Osaka University, Japan)
Gen Fujita	(Osaka Electro-Communication University, Japan)
Takao Onoye	(Osaka University, Japan)

A Hardware-oriented Intra Prediction Scheme for High Definition AVS Encoder (Abstract)

Man-Lan Wong	(National Taiwan University, Taiwan)
Yi-Lun Lin	(National Taiwan University, Taiwan)
Homer H. Chen	(National Taiwan University, Taiwan)

A 158 MS/S JPEG 2000 CODEC WITH A BIT-PLANE AND PASS PARALLEL EMBEDDED BLOCK CODER (Abstract)

LOW-POWER HIGH-THROUGHPUT MQ-CODER ARCHITECTURE WITH AN IMPROVED CODING ALGORITHM (Abstract)

Menu